MRAM BASED DESIGN, TEST AND RELIABILITY FOR ULTRA LOW POWER SoC – MASTA

The microelectronics industry will face major challenges related to power dissipation and energy consumption in the next years. Both static and dynamic consumption (already dominated by the leakage power) will soon start to limit microprocessor performance growth. A promising way to stop this trend is the integration of non-volatility as a new feature of memory caches, which would immediately minimize static power as well as paving the way towards normally-off/instant-on computing. The use of emerging spin-based non-volatile memory devices, aka Magnetic Random Access Memory (MRAM), in both memory hierarchy and logic (the so called “memory-in-logic”) of computing systems provides a huge opportunity for low-power systems.
The objective of this research project is to investigate, design, develop, and analyze hybrid CMOS-MRAM normally-off computing architectures in which MRAMs are used at various levels of the memory hierarchy (memory-in-logic, register files, different levels of cache, main memory) along with traditional CMOS devices and memories to achieve ultra-low-power and provide high performance and low cost. We plan to highlight the full potential of this technology by covering various aspects of the cell, array, memory hierarchy, and architecture design as well as fault modeling, design for test, reliability, and robustness. We will also develop a set of modeling, design, and simulation tools from circuit to system levels to design and evaluate hybrid memory hierarchies and processor architecture.