NEMS based adiabatic logic – ADIANEMS2

The ambition of the project is to obtain a radical (100-fold) reduction of the energy dissipation in a computing system. To this end, we propose a disruptive innovative approach, through association of adiabatic logic principles and NEMS (Nano-Electrical -Mechanical System) technology. Demonstration of the energy dissipation reduction will be achieved by modeling a medium complexity computing function (i.e. one adder or/and multiplier), whose building blocks will be experimentally validated. A promising solution is the adiabatic logic. In a conventional logic, the input of a logical gate changes abruptly from 0 to Vdd. In contrast, adiabatic gates do not switch abruptly and a voltage ramp (T is now the duration of the ramp) is used to pass from 0 to Vdd. It is easy to prove that the energy dissipation is now RC/T C·V^2 where R is the resistance of the switch in the conductive state. If the duration T is large compared to the product RC, an important decrease of the dissipation is possible. This does not mean that the operating frequency is low, because capacitance values of scaled devices are of a few fF and RC may be as small as one nanosecond. Thus, operating frequencies below 100 MHz seem realistic. For adiabatic logic implementation, two architectures have been investigated: the reversible pipeline and the quasi-adiabatic pipeline. Landauer in 1961 stated that computation energy must be dissipated if information is erased and demonstrated the interest of the reversible computing. This theorem explains that each erased bit generates a theoretical lower bound of kTln2 for dissipated energy. Unfortunately, reversible gates are different from conventional logic gates and a severe overhead (from 10 to 100) in term of gates number is introduced. Many designers have chosen to dismiss the reversible logic approach and preferred to implement a more realistic solution: the quasi-adiabatic pipeline. Unfavorably, implementations of such pipeline on silicon CMOS technology introduce a residual non-adiabatic dissipation C·Vt^2 where Vt is the threshold voltage of the CMOS technology. Consequently, energy dissipation is only reduced from C·Vdd^2 to C·Vt^2. It is not possible to choose a small enough value for Vt, as in that case the leakage current would strongly increase. The gain of CMOS adiabatic is consequently far from the theoretical limit. These limitations explain the reason why pure CMOS silicon technology is not the best choice for implementing adiabatic logic solutions. NEMS technology may circumvent this limitation, as described below. The second half of the 19th century was an active period for mechanical computing. A first calculator operated via a keyboard was developed in 1884. Electromechanical calculators were big machines limited in performances and power dissipation. Recently, scientists have resurrected mechanical computing. When a sufficiently large gate-to-source voltage is applied (above VPI), the electrostatic force is sufficient to establish the contact and the switch is turned to the on-state. As the gate voltage decreases below the release voltage (VRL), contact is broken and the switch is turned back to the off-state. This hysteresis behavior is due to surface adhesion energy during contact. If the typical size of the device is reduced at nanoscale (below one micron), the NEMS terminology is used instead of the MEMS terminology but actuation principles remain the same. Preliminary work on MEMS-based logic has started two decades ago [1] and it was proved for the first time in 2012 [2] that it is possible to implement adiabatic gates using NEMS relays. Contrarily to the CMOS solution, it is now possible to reduce the non-adiabatic dissipation C·V.RL^2 by lowering the release voltage VRL of the nanorelay without negative impact on the leakage current because the leakage is negligible.