DS07 - Société de l'information et de la communication

Secure and Trusted Analog Hardware Technology – STEALTH

Submission summary

Owing to various financial factors, the contemporary semiconductor industry relies on a complex business model, wherein the vast majority of circuit intellectual property (IP) design and integrated circuit (IC) fabrication activities are outsourced to third-party design houses and foundries. The globalized and highly distributed nature of third-party entities results in a semiconductor supply chain model which exhibits several vulnerable points during the design, fabrication, and even the deployment phase of an IC. These vulnerabilities may be exploited by a knowledgeable adversary, thereby introducing various trustworthiness and security threats to the semiconductor industry and the end IC users, namely IP/IC piracy, which includes reverse engineering and counterfeiting, hardware Trojans, side-channel attacks, and fault injection attacks.
While extensive research efforts have been expended over the last decade in understanding trust and security threat scenarios in digital ICs, as well as in developing prevention, countermeasure, and detection solutions, the topic remains largely unexplored for their analog counterparts. Analog ICs are considered nowadays as the weakest link in warranting the global security policy for the entire electronic system. In fact, the lack of understanding of the threat and solution space in the analog domain is alarming given the widespread use of analog ICs in most contemporary systems and given the forecast that the importance of analog ICs is expected to grow in the era of IoTs. By 2020, an estimate of more than 50 billion connected devices will include analog ICs for receiving and transmitting data and for interfacing physical sensor data to the digital microprocessor.
This project concerns hardware trust and security aspects specifically for analog ICs. The project seeks to understand the vulnerability of analog ICs to security breaches, as well as to propose remedies and methodologies toward designing, fabricating, and deploying trusted and secure analog ICs. More specifically, the project envisions developing a large portfolio of obfuscation methodologies for equipping analog ICs with a capability that prevents reverse engineering and counterfeiting.
Reverse engineering is conducted by an attacker to (a) gain information about the internal blocks of the IC (i.e., architecture, netlist, layout masks, implementation details, technological data, etc.) aiming at reducing the attacker’s technological disadvantage against the “author” of the IC; (b) gather necessary information for producing a counterfeit circuit; (c) gather valuable information for putting forward a successful and inescapable hardware attack; (d) locate the root-of-trust part of the IC so as to steal secret and sensitive information.
Counterfeiting refers to (a) illegal theft of the IC design aiming at producing and selling a similar or identical IC; (b) reselling as new a used, and possibly aged IC; (c) non contractual overproducing of ICs and illegitimate selling of these ICs by an untrusted foundry.
Reverse engineering and counterfeiting have become a target of intense scrutiny nowadays and addressing them efficiently is considered of major significance since they have serious implications on governments (i.e., threat to national security, loss of tax revenue, regulatory law enforcement, etc.), industry (i.e., loss of revenue, loss of know-how, loss of brand name, costs to mitigate risks, etc.), and the consumers and society as a whole (i.e., safety concerns, costs for replacing failed or low-quality products, etc.).
The developed obfuscation methodologies will range from generic ones, which are virtually applicable to any circuit class, to circuit class-specific ones, which are applicable to all architectures within a specific circuit class. Comprehensive metrics will be developed to quantify the security protection level achieved, the intrusiveness into the design, the incurred area overhead, etc.

Project coordination

Haralampos Stratigopoulos (Laboratoire d'Informatique de Paris 6)

The author of this summary is the project coordinator, who is responsible for the content of this summary. The ANR declines any responsibility as for its contents.

Partner

LIP6 - UPMC Laboratoire d'Informatique de Paris 6

Help of the ANR 248,620 euros
Beginning and duration of the scientific project: - 36 Months

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